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dual 12-/14-/16-bit nano dac ? with 5 ppm/c on-chip reference ad5623r/ad5643r/ad5663r rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2011 analog devices, inc. all rights reserved. features low power, smallest pin-compatible, dual nano dac ad5663r: 16 bits ad5643r: 14 bits ad5623r: 12 bits user-selectable external or internal reference external reference default on-chip 1.25 v/2.5 v, 5 ppm/c reference 10-lead msop and 3 mm 3 mm lfcsp 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale per channel power-down serial interface up to 50 mhz hardware ldac and clr functions applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram interface logic sclk sync din clr input register input register dac register dac register v dd gnd power-on reset string dac a string dac b buffer buffer v refin / v refout power-down logic v out a v out b ad5623r/ad5643r/ad5663r ldac ldac 05858-001 1.25v/2.5v reference figure 1. table 1. related devices part no. description ad5663 2.7 v to 5.5 v, dual 16-bit nano dac, with external reference general description the ad5623r/ad5643r/ad5663r, members of the nano dac family, are low power, dual 12-, 14-, and 16-bit buffered voltage- out digital-to-analog converters (dac) that operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5623r/ad5643r/ad5663r have an on-chip reference. the ad5623r-3/ad5643r-3/ad5663r-3 have a 1.25 v, 5 ppm/c reference, giving a full-scale output of 2.5 v; and the ad5623r-5/ ad5643r-5/ad5663r-5 have a 2.5 v, 5 ppm/c reference, giving a full-scale output of 5 v. the on-chip reference is off at power-up, allowing the use of an external reference; and all devices can be operated from a single 2.7 v to 5.5 v supply. the internal reference is turned on by writing to the dac. the parts incorporate a power-on reset circuit that ensures the dac output powers up to 0 v and remains there until a valid write takes place. the part contains a power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power- down mode. the low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. the ad5623r/ad5643r/ad5663r use a versatile, 3-wire serial interface that operates at clock rates up to 50 mhz, and they are compatible with standard spi?, qspi?, microwire?, and dsp interface standards. the on-chip precision output amplifier enables rail-to-rail output swing to be achieved. product highlights 1. dual 12-, 14-, and 16-bit dac. 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 10-lead msop and 10-lead, 3 mm 3 mm lfcsp. 4. low power; typically consumes 0.6 mw at 3 v and 1.25 mw at 5 v. 5. 4.5 s maximum settling time for the ad5623r.
ad5623r/ad5643r/ad5663r rev. d | page 2 of 32 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? ad5623r-5/ad5643r-5/ad5663r-5 ....................................... 3 ? ad5623r-3/ad5643r-3/ad5663r-3 ....................................... 5 ? ac characteristics........................................................................ 6 ? timing characteristics ................................................................ 7 ? timing diagram ........................................................................... 7 ? absolute maximum ratings............................................................ 8 ? esd caution.................................................................................. 8 ? pin configuration and function descriptions............................. 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 18 ? theory of operation ...................................................................... 20 ? digital-to-analog section ......................................................... 20 ? resistor string ............................................................................. 20 ? output amplifier........................................................................ 20 ? internal reference ...................................................................... 20 ? external reference ..................................................................... 20 ? serial interface ............................................................................ 20 ? input shift register .................................................................... 21 ? sync interrupt .......................................................................... 21 ? power-on reset.......................................................................... 22 ? software reset............................................................................. 22 ? power-down modes .................................................................. 22 ? ldac function .......................................................................... 23 ? internal reference setup ........................................................... 24 ? microprocessor interfacing....................................................... 25 ? applications information .............................................................. 26 ? using a reference as a power supply....................................... 26 ? bipolar operation using the ad5663r .................................. 26 ? using the ad5663r with a galvanically isolated interface . 26 ? power supply bypassing and grounding................................ 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 29 ? revision history 4/11rev. c to rev. d changes to ordering guide .......................................................... 29 6/10rev. b to rev. c changes to ordering guide .......................................................... 28 4/10rev. a to rev. b updated outline dimensions ....................................................... 28 12/06rev. 0 to rev. a changes to table 2.............................................................................3 changes to table 3.............................................................................5 changes to figure 3...........................................................................9 changes to ordering guide .......................................................... 28 4/06revision 0: initial version
ad5623r/ad5643r/ad5663r rev. d | page 3 of 32 specifications ad5623r-5/ad5643r-5/ad5663r-5 v dd = 4.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max, unless otherwise noted. table 2. b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5663r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5643r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5623r resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-scale error +2 +10 mv all 0s loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all 1s loaded to dac register gain error 1.5 % of fsr zero-scale error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale ; v dd = 5 v 10% dc crosstalk (external reference) 10 v due to full-scale output change; r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) dc crosstalk (internal reference) 25 v due to full-scale output change; r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short-circuit current 30 ma v dd = 5 v power-up time 4 s coming out of power-down mode; v dd = 5 v reference inputs reference current 170 200 a v ref = v dd = 5.5 v reference input range 0.75 v dd v reference input impedance 26 k reference output output voltage 2.495 2.505 v at ambient reference temperature coefficient 3 5 10 ppm/c msop package models 10 ppm/c lfcsp package models output impedance 7.5 k
ad5623r/ad5643r/ad5663r rev. d | page 4 of 32 b grade 1 parameter min typ max unit conditions/comments logic inputs 3 input current 2 a all digital inputs input low voltage (v inl ) 0.8 v v dd = 5 v input high voltage (v inh ) 2 v v dd = 5 v pin capacitance 3 pf din, sclk, and sync 19 pf ldac and clr power requirements v dd 4.5 5.5 v i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.25 0.45 ma internal reference off v dd = 4.5 v to 5.5 v 0.8 1 ma internal reference on i dd (all power-down modes) 5 v dd = 4.5 v to 5.5 v 0.48 1 a v ih = v dd and v il = gnd 1 temperature range: b gra de = ?40c to +105c. 2 linearity calculated using a reduced code range: ad 5663r (code 512 to code 65,024), ad5643r (code 128 to code 16,256), and ad5 623r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 both dacs powered down.
ad5623r/ad5643r/ad5663r rev. d | page 5 of 32 ad5623r-3/ad5643r-3/ad5663r-3 v dd = 2.7 v to 3.6 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 3. b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5663r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5643r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5623r resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-scale error +2 +10 mv all 0s loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all 1s loaded to dac register gain error 1.5 % of fsr zero-scale error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale; v dd = 3 v 10% dc crosstalk (external reference) 10 v due to full-scale output change; r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) dc crosstalk (internal reference) 25 v due to full-scale output change; r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short circuit current 30 ma v dd = 3 v power-up time 4 s coming out of power-down mode; v dd = 3 v reference inputs reference current 170 200 a v ref = v dd = 3.6 v reference input range 0.75 v dd v reference input impedance 26 k reference output output voltage 1.247 1.253 v at ambient reference temperature coefficient 3 5 15 ppm/c msop package models 10 ppm/c lfcsp package models output impedance 7.5 k
ad5623r/ad5643r/ad5663r rev. d | page 6 of 32 b grade 1 parameter min typ max unit conditions/comments logic inputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 3 v v inh , input high voltage 2 v v dd = 3 v pin capacitance 3 pf din, sclk, and sync 19 pf ldac and clr power requirements v dd 2.7 3.6 v i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 200 425 a internal reference off v dd = 2.7 v to 3.6 v 800 900 a internal reference on i dd (all power-down modes) 5 v dd = 2.7 v to 3.6 v 0.2 1 a v ih = v dd and v il = gnd 1 temperature range: b gra de = ?40c to +105c. 2 linearity calculated using a reduced code range: ad 5663r (code 512 to code 65,024), ad5643r (code 128 to code 16,256), and ad5 623r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 both dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 4. parameter 1 , 2 min typ max unit conditions/comments 3 output voltage settling time ad5623r 3 4.5 s ? to ? scale settling to 0.5 lsb ad5643r 3.5 5 s ? to ? scale settling to 0.5 lsb ad5663r 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry digital feedthrough 0.1 nv-s reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv-s analog crosstalk 1 nv-s external reference 4 nv-s internal reference dac-to-dac crosstalk 1 nv-s external reference 4 nv-s internal reference multiplying bandwidth 340 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = midscale, 1 khz 100 nv/hz dac code = midscale, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range: b grade = ?40 c to +105c, typical at +25c.
ad5623r/ad5643r/ad5663r rev. d | page 7 of 32 timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. 1 table 5. limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 2 20 ns min sclk cycle time t 2 9 ns min sclk high time t 3 9 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore t 11 10 ns min ldac pulse width low t 12 15 ns min sclk falling edge to ldac rising edge t 13 5 ns min clr pulse width low t 14 0 ns min sclk falling edge to ldac falling edge t 15 300 ns max clr pulse activation time 1 guaranteed by design and characterization, not production tested. 2 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. timing diagram 05858-002 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 t 12 ldac 1 ldac 2 t 14 1 asynchronous ldac update mode. 2 synchronous ldac update mode. clr t 13 t 15 v out db0 figure 2. serial write operation
ad5623r/ad5643r/ad5663r rev. d | page 8 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja lfcsp package (4-layer board) ja thermal impedance 61c/w msop package (4-layer board) ja thermal impedance 142c/w jc thermal impedance 43.7c/w reflow soldering peak temperature pb-free 260(+0/?5)c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5623r/ad5643r/ad5663r rev. d | page 9 of 32 pin configuration and fu nction descriptions 05858-003 1 v out a 10 v refin /v refout 2 v out b 9 v dd 3 gnd 8 din 4 ldac 7 sclk 5 clr 6 sync ad5623r/ ad5643r/ ad5663r top view (not to scale) note: exposed pad tied to gnd on lfcsp package. figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 2 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 3 gnd ground. reference point for all circuitry on the part. 4 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 5 clr asynchronous clear input. the clr input is falling edge sensitive. while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the 24th falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. 6 sync level-triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. the dac is updated following the 24th clock cycle unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. 7 sclk serial clock input. data is clocked into the input shift register on the falli ng edge of the serial clock input. data can be transferred at rates up to 50 mhz. 8 din serial data input. this device has a 24-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 9 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 10 v refin /v refout common reference input/reference output. when the internal reference is selected, this is the reference output pin. when using an external reference, this is the referenc e input pin. the default for this pin is a reference input.
ad5623r/ad5643r/ad5663r rev. d | page 10 of 32 typical performance characteristics code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k v dd = v ref = 5v t a = 25c 05858-008 code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k v dd = v ref = 5v t a = 25c 05858-005 figure 7. dnlad5663r, external reference figure 4. inlad5663r, external reference dnl error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 v dd = v ref = 5v t a = 25c code 0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k 05858-009 code inl error (lsb) 4 ?4 0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c 05858-006 figure 8. dnlad5643r, external reference figure 5. inlad5643r, external reference code inl error (lsb) 1.0 ?1.0 0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c 05858-007 dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 code 0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k v dd = v ref = 5v t a = 25c 0 5858-010 figure 6. inlad5623r, external reference figure 9. dnlad5623r, external reference
ad5623r/ad5643r/ad5663r rev. d | page 11 of 32 code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 v dd = 5v v refout = 2.5v t a = 25c 05858-011 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k figure 10. inlad5663r-5 code inl error (lsb) 4 3 ?4 ?3 ?2 2 ?1 1 0 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 0 5858-012 figure 11. inlad5643r-5 code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 01 . 0 k 0.5k 2.0k 1.5k 3.5k 3.0k 2.5k 4.0k v dd = 5v v refout = 2.5v t a = 25c 0 5858-013 figure 12. inlad5623r-5 code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65k 60k 55k 50k 45k 40k 35k 30k 25k 20k 15k 10k5k 0 v dd = 5v v refout = 2.5v t a = 25c 05858-014 figure 13. dnlad5663r-5 code dnl error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 0 5858-015 figure 14. dnlad5643r-5 code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 01 . 0 k 0.5k 2.0k 1.5k 3.5k 3.0k 2.5k 4.0k v dd = 5v v refout = 2.5v t a = 25c 0 5858-016 figure 15. dnlad5623r-5
ad5623r/ad5643r/ad5663r rev. d | page 12 of 32 code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 05858-017 v dd = 3v v refout = 1.25v t a = 25c 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k figure 16. inlad5663r-3 code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 3 2 1 0 ?1 ?2 ?3 05858-018 v dd = 3v v refout = 1.25v t a = 25c figure 17. inlad5643r-3 code inl error (lsb) 1.0 ?1.0 0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 05858-019 v dd = 3v v refout = 1.25v t a = 25c figure 18. inlad5623r-3 code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 05858-020 v dd = 3v v refout = 1.25v t a = 25c 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k figure 19. dnlad5663r-3 code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 05858-021 v dd = 3v v refout = 1.25v t a = 25c figure 20. dnlad5643r-3 code dnl error (lsb) 0.20 ?0.20 0 0.5k1.0k1.5k2.0k2.5k3.0k3.5k4.0k 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 05858-022 v dd = 3v v refout = 1.25v t a = 25c figure 21. dnlad5623r-3
ad5623r/ad5643r/ad5663r rev. d | page 13 of 32 temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 20 01 8060 120 05858-080 0 0 min dnl max dnl max inl min inl v dd = v ref = 5v figure 22. inl error and dnl error vs. temperature v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 05858-081 min dnl max dnl max inl min inl v dd = 5v t a = 25c figure 23. inl error and dnl error vs. v ref v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 05858-082 min dnl max dnl max inl min inl t a = 25c figure 24. inl error and dnl error vs. supply temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 v dd = 5v gain error full-scale error 05858-023 figure 25. gain error and full-scale error vs. temperature temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 60 100 0 offset error zero-scale error 05858-024 figure 26. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 05858-025 figure 27. gain error and full-scale error vs. supply
ad5623r/ad5643r/ad5663r rev. d | page 14 of 32 v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 05858-026 figure 28. zero-scale error and offset error vs. supply i dd (ma) number of units 8 6 4 2 0 0.230 0.235 0.240 0.245 0.250 0.255 v dd = 5.5v t a = 25c 05858-090 figure 29. i dd histogram with external reference i dd (ma) number of units 4 5 3 2 1 0 0.78 0.80 0.82 0.84 v dd = 5.5v t a = 25c 05858-091 figure 30. i dd histogram with internal reference current (ma) error voltage (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 61 0 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 0 5858-029 figure 31. headroom at rails vs. source and sink current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25 c zero scale full scale midscale 1/4 scale 3/4 scale 0 5858-030 figure 32. ad56x3r-5 sour ce and sink capability current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 5858-031 figure 33. ad56x3r-3 sour ce and sink capability
ad5623r/ad5643r/ad5663r rev. d | page 15 of 32 temperature (c) i dd (ma) 0.30 0.05 0.10 0.15 0.20 0.25 0 ?40 ?20 0 20 40 60 80 100 05858-044 t a = 25c v dd = v refin = 5v v dd = v refin = 3v figure 34. supply current vs. temperature time base = 4s/div v dd = v ref = 5v t a = 25c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 05858-060 figure 35. full-scale settling time, 5 v ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25c v out v dd 1 2 max(c2)* 420.0mv 05858-061 figure 36. power-on reset to 0 v v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 05858-062 figure 37. exiting po wer-down to midscale sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 05858-058 v dd = v ref = 5v t a = 25c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) figure 38. digital-to-analog glitch impulse (negative) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 05858-059 v dd = v ref = 5v t a = 25c 5ns/sample number analog crosstalk = 0.424nv figure 39. analog crosstalk, external reference
ad5623r/ad5643r/ad5663r rev. d | page 16 of 32 sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 05858-057 v dd = 5v v refout = 2.5v t a = 25c 5ns/sample number analog crosstalk = 4.462nv figure 40. analog crosstalk, internal reference 1 y axis = 2v/div x axis = 4s/div v dd = v ref = 5v t a = 25c dac loaded with midscale 05858-063 figure 41. 0.1 hz to 10 hz output noise plot, external reference 5s/div 10v/di v 1 v dd = 5v v refout = 2.5v t a = 25c dac loaded with midscale 05858-064 figure 42. 0.1 hz to 10 hz outp ut noise plot, internal reference 4s/div 5v/di v 1 v dd = 3v v refout = 1.25v t a = 25c dac loaded with midscale 05858-065 figure 43. 0.1 hz to 10 hz output noise plot, internal reference frequency (hz) output noise (nv/ hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 1m 10m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 0 5858-066 figure 44. noise spectral density, internal reference frequency (hz) (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p 0 5858-067 figure 45. total harmonic distortion
ad5623r/ad5643r/ad5663r rev. d | page 17 of 32 0 capacitance (nf) time (s) 16 14 12 10 8 6 4 012 34567 9 81 v ref = v dd t a = 25c v dd = 5v v dd = 3v 0 5858-068 05858-050 v out a v out b 3 ch3 5.0v ch4 1.0v ch2 1.0v m200ns a ch3 1.10v 2 4 4 clr figure 48. clr pulse activation time figure 46. settling time vs. capacitive load frequency (hz) (db) 5 ?40 10k 100k 1m 10m ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 05858-069 v dd = 5v t a = 25c figure 47. multiplying bandwidth
ad5623r/ad5643r/ad5663r rev. d | page 18 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 5 . differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot is shown in figure 9 . zero-scale error zero-scale error is the measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-scale error is always positive in the ad56x3r because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and the output amplifier. zero-scale error is expressed in mv. a plot of zero-scale error vs. temperature is shown in figure 26 . full-scale error full-scale error is the measurement of the output error when full-scale code (0xffff) is loaded into the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error vs. temperature is shown in figure 25 . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full-scale range. zero-scale error drift zero-scale error drift is the measurement of the change in zero- scale error with a change in temperature. it is expressed in microvolts/c (v/c). gain temperature coefficient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad56x3r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in vout to a change in vdd for full-scale output of the dac. it is measured in db. vref is held at 2 v, and vdd is varied by 10%. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the 24th falling edge of sclk. digital-to-analog glitch impulse the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 38 . digital feedthrough a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, digital feedthrough is measured when the dac output is not updated. it is specified in nv-s, and it is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels (db). noise spectral density noise spectral density is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. a plot of noise spectral density is shown in figure 44 . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in microvolts (v). dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts/ milliamps (v/ma).
ad5623r/ad5643r/ad5663r rev. d | page 19 of 32 digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nanovolts-second (nv-s). analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nanovolts-second (nv-s). dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nanovolts-second (nv-s). multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in decibels (db).
ad5623r/ad5643r/ad5663r rev. d | page 20 of 32 theory of operation digital-to-analog section the ad5623r/ad5643r/ad5663r dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 49 shows a block diagram of the dac architecture. dac register resistor string ref (+) v dd gnd ref (?) v out output amplifier (gain = +2) 05858-032 figure 49. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d vv 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for ad5623r (12-bit) 0 to 16,383 for ad5643r (14-bit) 0 to 65,535 for ad5663r (16-bit) n is the dac resolution. resistor string the resistor string section is shown in figure 50 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 31 . the slew rate is 1.8 v/s with a 1/4 to 3/4 full-scale settling time of 10 s. r r r r r to output amplifier 0 5858-033 figure 50. resistor string internal reference the ad5623r/ad5643r/ad5663r on-chip reference is off at power-up and is enabled via a write to a control register. see the internal reference setup section for details. the ad56x3r-3 has a 1.25 v, 5 ppm/c reference, giving a full- scale output of 2.5 v. the ad56x3r-5 has a 2.5 v, 5 ppm/c reference, giving a full-scale output of 5 v. the internal refer- ence associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor be placed between reference output and gnd for reference stability. external reference the v refin pins on the ad56x3r-3 and the ad56x3r-5 allows the use of an external reference if the application requires it. the on-chip reference is off at power-up, and this is the default condition. the ad56x3r-3 and th e ad56x3r-5 can be operated from a single 2.7 v to 5.5 v supply. serial interface the ad5623r/ad5643r/ad5663r have a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards, as well as with most dsps. see for a timing diagram of a typical write sequence. figure 2 the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5623r/ad5643r/ad5663r compatible with high speed dsps. on the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, for example, a change in dac register contents and/or a change in the mode of operation.
ad5623r/ad5643r/ad5663r rev. d | page 21 of 32 at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence, so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation. as mentioned previously, it must, however, be brought high again just before the next write sequence. input shift register the input shift register is 24 bits wide (see figure 52 ). the first two bits are dont cares. the next three are command bit c2 to command bit c0 (see tabl e 8 ), followed by the 3-bit dac address a2 to dac address a0 (see table 9 ), and, finally, the 16-, 14-, and 12-bit data-word. the data-word comprises the 16-, 14-, and 12-bit input codes, followed by zero, two, or four dont care bits, for the ad5663r, ad5643r, and ad5623r, respectively (see figure 51 , figure 52 , and figure 53 ). the data bits are transferred to the dac register on the 24th falling edge of sclk. table 8. command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n , update all (software ldac ) 0 1 1 write to and update dac channel n 1 0 0 power down dac (power up) 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on/off ) table 9. address command a2 a1 a0 address (n) 0 0 0 dac a 0 0 1 dac b 0 1 0 reserved 0 1 1 reserved 1 1 1 all dacs sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24th falling edge. however, if sync is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see ). figure 54 x x c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05858-034 figure 51. ad5663r input shift register contents x x c2 c1 c0 a2 a1 a0 xx d11 d10 d13 d12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05858-071 figure 52. ad5643r input shift register contents x x c2 c1 c0 a2 a1 a0 xxxx d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05858-072 figure 53. ad5623r input shift register contents din db23 db23 db0 db0 valid write sequence, output updates on the 24 th falling edge s ync sclk invalid write sequence: sync high before 24 th falling edge 05858-035 figure 54. sync interrupt facility
ad5623r/ad5643r/ad5663r rev. d | page 22 of 32 power-on reset the ad5623r/ad5643r/ad5663r contain a power-on reset circuit that controls the output voltage during power-up. the ad5623r/ad5643r/ad5663r dacs output power up to 0 v, and the output remains there until a valid write sequence is made to the dacs. this is useful in applications where it is important to know the state of the output of the dacs while they are in the process of powering up. any events on ldac or clr during power-on reset are ignored. software reset the ad5623r/ad5643r/ad5663r contain a software reset function. command 101 is reserved for the software reset function (see table 8 ). the software reset command contains two reset modes that are software-programmable by setting bit db0 in the control register. table 10 shows how the state of the bit corresponds to the mode of operation of the device. table 1 2 shows the contents of the input shift register during the software reset mode of operation. table 10. software reset modes db0 registers reset to zero 0 dac register input register 1 (power-on reset) dac register input register ldac register power-down register internal reference setup register power-down modes the ad5623r/ad5643r/ad5663r contain four separate modes of operation. command 100 is reserved for the power- down function (see table 8 ). these modes are software- programmable by setting bit db5 and bit db4 in the control register. table 1 1 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac b and dac a) can be powered down to the selected mode by setting the corresponding two bits (bit db1 and bit db0) to 1. by executing the same command 100, any combination of dacs can be powered up by setting bit db5 and bit db4 to normal operation mode. again, to select which combination of dac channels to power up, set the corresponding bits (bit db1 and bit db0) to 1. see table 13 for contents of the input shift register during power- down/power-up operation. the dac output powers up to the value in the input register while ldac is low. if ldac is high, the dac ouput powers up to the value held in the dac register before power-down. table 11. modes of operation db5 db4 operating mode 0 0 normal operation power-down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state when both bit db1 and bit db2 are set to 0, the part works normally, with its normal power consumption of 250 a at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. the outputs can either be connected internally to gnd through a 1 k or 100 k resistor or left open-circuited (three-state) (see figure 55 ). resistor network v out resistor string dac power-down circuitry amplifier 05858-036 figure 55. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for both vdd = 5 v and vdd = 3 v (see figure 37 ). table 12. 24-bit input shift register contents for software reset command msb lsb db23 to db22 db21 db20 db19 db 18 db17 db16 db15 to db1 db0 x 1 0 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0) dont care determines software reset mode
ad5623r/ad5643r/ad5663r rev. d | page 23 of 32 table 13. 24-bit input shift register contents of power up/down function msb lsb db23 to db22 db21 db20 db 19 db18 db17 db16 db15 to db6 db5 db4 db3 db2 db1 db0 x 1 0 0 x x x x pd1 pd0 x x dac b dac a dont care command bits (c2 to c0) address bits (a2 to a0) dont care dont care power-down mode dont care power down/power up channel selection; set bit to 1 to select channel table 14. 24-bit input shift register contents for ldac setup command msb lsb db23 to db22 db21 db20 db19 db110 db17 db16 db15 to db2 db1 db0 x 1 1 0 x x x x dac b dac a dont care command bits (c2 to c0) address bits (a3 to a0) dont care dont care set dac to 0 or 1 for required mode of operation ldac function the ad5623r/ad5643r/ad5663r dacs have double- buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when the ldac pin is high, the dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when ldac is brought low, however, the dac registers become transparent and the contents of the input registers are transferred to them. the double-buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user can write to one of the input registers individually and then, by bringing ldac low when writing to the other dac input register, all outputs will update simultaneously. these parts each contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5623r/ad5643r/ ad5663r, the dac register updates only if the input register has changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. the outputs of all dacs can be simultaneously updated, using the hardware ldac pin. synchronous ldac the dac registers are updated after new data is read in on the falling edge of the 24th sclk pulse. ldac can be permanently low or pulsed as shown in . figure 2 asynchronous ldac the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. the ldac register gives the user full flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that the update of this channel is controlled by the ldac pin. if this bit is set to 1, this channel synchronously updates; that is, the dac register is updated after new data is read in, regardless of the state of the ldac pin. it effectively sees the ldac pin as being pulled low. see for the table 15 ldac register mode of operation. this flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 110 loads the 2-bit ldac register [db1:db0]. the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 means the dac register is updated, regardless of the state of the ldac pin. see for contents of the input shift register during the tabl e 14 ldac register setup command. table 15. ldac register mode of operation ldac bits (db1 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin 1 x = dont care the dac registers are updated after new data is read in on the falling edge of the 24th sclk pulse.
ad5623r/ad5643r/ad5663r rev. d | page 24 of 32 internal reference setup the on-chip reference is off at power-up by default. this reference can be turned on or off by setting a software programmable bit, db0, in the control register. table 16 shows how the state of the bit corresponds to the mode of operation. command 111 is reserved for setting up the internal reference (see table 8 ). see table 16 for the contents of the input shift register during the internal reference setup command. table 16. reference setup register internal reference setup register (db0) action 0 reference off (default) 1 reference on table 17. 32-bit input shift register contents for reference setup function msb lsb db23 to db22 db21 db20 db19 db 18 db17 db16 db15 to db1 db0 x 1 1 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0) dont care reference setup register
ad5623r/ad5643r/ad5663r rev. d | page 25 of 32 microprocessor interfacing ad5623r/ad5643r/ad5663r to blackfin? adsp-bf53x interface figure 56 shows a serial interface between the ad5623r/ ad5643r/ad5663r and the blackfin adsp-bf53x micro- processor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5623r/ad5643r/ad5663r, the setup for the interface is as follows: dt0pri drives the din pin of the ad5623r/ad5643r/ad5663r, while tsclk0 drives the sclk of the parts. the sync is driven from tfs0. ad5643r/ ad5663r 1 adsp-bf53x 1 sync tfs0 din dtopri sclk tsclk0 1 additional pins omitted for clarity. 05858-037 figure 56. ad5623r/ad5643r/ad5663r to blackfin adsp-bf53x interface ad5623r/ad5643r/ad5663r to 68hc11/68l11 interface figure 57 shows a serial interface between the ad5623r/ ad5643r/ad5663r and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5623r/ ad5643r/ad5663r, and the mosi output drives the serial data line of the dac. ad5643r/ ad5663r 1 68hc11/68l11 1 sync pc7 sclk sck din mosi 1 additional pins omitted for clarity. 05858-038 figure 57. ad5623r/ad5643r/ad5663r to 68hc11/68l11 interface the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 is configured with its cpol bit as 0, and its cpha bit as 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as described previously, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5623r/ ad5643r/ad5663r, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. ad5623r/ad5643r/ad5663r to 80c51/80l51 interface figure 58 shows a serial interface between the ad5623r/ ad5643r/ad5663r and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/ 80l51 drives sclk of the ad5623r/ad5643r/ad5663r, and rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5623r/ad5643r/ad5663r, p3.3 is taken low. the 80c51/ 80l51 transmit data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data in a format that has the lsb first. the ad5623r/ad5643r/ad5663r must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. ad5643r/ ad5663r 1 80c51/80l51 1 sync p3.3 sclk txd din rxd 1 additional pins omitted for clarity. 05858-039 figure 58. ad5623r/ad5643r/ad5663r to 80c512/80l51 interface ad5623r/ad5643r/ad5663r to microwire interface figure 59 shows an interface between the ad5623r/ad5643r/ ad5663r and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5623r/ad5643r/ad5663r on the rising edge of the sk. ad5643r/ ad5663r 1 microwire 1 sync cs sclk sk din so 1 additional pins omitted for clarity. 05858-040 figure 59. ad5623r/ad5643r/ad5663r to microwire interface
ad5623r/ad5643r/ad5663r rev. d | page 26 of 32 applications information using a reference as a power supply because the supply current required by the ad5623r/ad5643r/ ad5663r is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see figure 60 ). this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad5623r/ad5643r/ ad5663r. if the low dropout ref195 is used, it must supply 500 a of current to the ad5623r/ad5643r/ad5663r, with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 500 a + (5 v/5 k) = 1.25 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in a 3 ppm (15 v) error for the 1.5 ma current drawn from it. this corresponds to a 0.196 lsb error. ad5623r/ ad5643r/ ad5663r t hree-wire serial interface sync sclk din 15 v 5v v out = 0v to 5v v dd ref195 05858-041 figure 60. ref195 as power supply to the ad5623r/ad5643r/ad5663r bipolar operation using the ad5663r the ad5663r has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 61 . the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd o 536,65 where d represents the input code in decimal (0 to 65,535). with v dd = 5 v, r1 = r2 = 10 k, v5 536,65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. three-wire serial interface r2 = 10k ? +5v ?5v ad820/ op295 +5v ad5663r v dd v out r1 = 10k ? 5v 0.1f 10f 05858-042 figure 61. bipolar operation with the ad5663r using the ad5663r with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that can occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. the ad5663r uses a 3-wire serial logic interface, so the adum1300 3-channel digital isolator provides the required isolation (see figure 62 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5663r. 0.1f 5v regulator gnd din sync sclk power 10f sdi sclk data ad5663r v out v ob v oa v oc v dd v ic v ib v ia adum1300 05858-043 figure 62. ad5663r with a galvanically isolated interface
ad5623r/ad5643r/ad5663r rev. d | page 27 of 32 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5663r should have separate analog and digital sections, each having its own area of the board. if the ad5663r is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5663r. the power supply to the ad5663r should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), which is found, for example, in common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
ad5623r/ad5643r/ad5663r rev. d | page 28 of 32 outline dimensions 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 63. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm x 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 64. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters
ad5623r/ad5643r/ad5663r rev. d | page 29 of 32 ordering guide model 1 temperature range accuracy internal reference package description package option branding ad5623rbcpz-3r2 ?40c to +105c 1 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d85 ad5623rbcpz-3reel7 ?40c to +105c 1 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d85 ad5623rbcpz-5reel7 ?40c to +105c 1 lsb inl 2.5 v 10-lead lfcsp_wd cp-10-9 d86 ad5623rbrmz-3 ?40c to +105c 1 lsb inl 1.25 v 10-lead msop rm-10 d85 ad5623rbrmz-3reel7 ?40c to +105c 1 lsb inl 1.25 v 10-lead msop rm-10 d85 ad5623rbrmz-5 ?40c to +105c 1 lsb inl 2.5 v 10-lead msop rm-10 d86 AD5623RBRMZ-5REEL7 ?40c to +105c 1 lsb inl 2.5 v 10-lead msop rm-10 d86 ad5643rbrmz-3 ?40c to +105c 4 lsb inl 1.25 v 10-lead msop rm-10 d81 ad5643rbrmz-3reel7 ?40c to +105c 4 lsb inl 1.25 v 10-lead msop rm-10 d81 ad5643rbrmz-5 ?40c to +105c 4 lsb inl 2.5 v 10-lead msop rm-10 d7q ad5643rbrmz-5reel7 ?40c to +105c 4 lsb inl 2.5 v 10-lead msop rm-10 d7q ad5663rbcpz-3r2 ?40c to +105c 16 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d7s ad5663rbcpz-3reel7 ?40c to +105c 16 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d7s ad5663rbcpz-5reel7 ?40c to +105c 16 lsb inl 2.5 v 10-lead lfcsp_wd cp-10-9 d3v ad5663rbrmz-3 ?40c to +105c 16 lsb inl 1.25 v 10-lead msop rm-10 d7s ad5663rbrmz-3reel7 ?40c to +105c 16 lsb inl 1.25 v 10-lead msop rm-10 d7s ad5663rbrmz-5 ?40c to +105c 16 lsb inl 2.5 v 10-lead msop rm-10 d7h ad5663rbrmz-5reel7 ?40c to +105c 16 lsb inl 2.5 v 10-lead msop rm-10 d7h eval-ad5663rebz evaluation board 1 z = rohs compliant part.
ad5623r/ad5643r/ad5663r rev. d | page 30 of 32 notes
ad5623r/ad5643r/ad5663r rev. d | page 31 of 32 notes
ad5623r/ad5643r/ad5663r rev. d | page 32 of 32 notes ?2006C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05858-0-4/11(d)

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